发明名称 |
Scan testing integrated circuits |
摘要 |
A test circuit and test technique for scan testing integrated circuits is disclosed. The test circuit includes a drive 1 or drive 0 scan element which utilizes fewer transistors than conventional scan latches. The testing technique utilizes the clock input to the latches in the ICs for propagating data through the latches. The test circuit and test techniques are highly advantageous for use with microprocessors and particularly RISC microprocessors. The test technique includes coupling a drive 1 or drive 0 element to a logic element coupled to a general latch. The drive 1 or drive 0 scan element allows the general latch to be clocked by a clock signal such as a phi 1 clock signal or phi 2 clock signal. <IMAGE> |
申请公布号 |
EP0600594(B1) |
申请公布日期 |
1998.03.04 |
申请号 |
EP19930307968 |
申请日期 |
1993.10.07 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
GANAPATHY, GOPI;THADEN, ROBERT;HORNE, STEVE |
分类号 |
G01R31/28;G01R31/3185;(IPC1-7):G06F11/26 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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