| 摘要 |
A lock detector suitable for detecting when an output signal of a phase-locked loop circuit is phase-locked to an input reference signal. The lock detector includes a pair of delay lines, that are adjustable, which are used to create a window signal around the reference clock signal. UP and DOWN signals from the PLL circuit are fed to an OR gate to generate an actual out-of-lock signal. When the PLL circuit is phase-locked within an acceptable phase error range, the UP, and DOWN signals, if any, will appear within the generated window signal. When the PLL circuit is not phase-locked within the acceptable phase error range, the UP, and DOWN signals occur outside of the window. The window signal, and the output of the OR gate are connected to an AND gate to generate a gated out-of-lock signal. The gated out-of-lock signal is connected to a switched-capacitor charge pump. So long as the switched-capacitor charge pump does not receive an active gated out-of-lock signal, the charge pump will, after a predetermined number of input clock signals, generate a logical lock signal, indicating that the PLL circuit has reached steady-state phase-lock. However, when the switched-capacitor charge pump receives an activated gated out-of-lock signal, the charge pump will deassert the logical lock signal.
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