Accelerated booth multiplier using interleaved operand loading

摘要

A multiplier which uses Booth recoding to multiply large word length operands. A first operand is fully loaded into a shift register. The loading of the second operand is then begun, with the recoding operation beginning after the loading of the minimum number of bits of the second operand required for the first stage of the recoding. The loading of the second operand continues while the previously loaded portions of the operand are recoded and the partial products based on those recoded portions are generated and accumulated.