SYSTEM VOLTAGES FOR EMITTER COUPLED LOGIC (ECL)-COMPATIBLE INPUT AND OUTPUT CIRCUITS IN CMOS TECHNOLOGY

摘要

In a circuit system in which CMOS (Complementary Metal Oxide Silicon) circuits and ECL (Emitter Coupled Logic) circuits cooperate, the CMOS circuit operating voltage terminal having the low potential GND is connected to the ECL circuit output operating voltage terminal having the potential VTT, and the CMOS circuit operating voltage terminal having the high potential VDD is connected to the ECL circuit operating voltage terminal having the potential VDD. The arrangement of the system voltages enables signals to be transmitted beyond subassemblies at high speed and with low losses and avoiding the use of suppressor circuits.