METHOD FOR DESIGNING LAYOUT AND WIRING OF INTEGRATED CIRCUIT,申请号JP19960204017-传众专利搜索

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发明名称	METHOD FOR DESIGNING LAYOUT AND WIRING OF INTEGRATED CIRCUIT
摘要
申请公布号	JPH1050848(A)	申请公布日期	1998.02.20
申请号	JP19960204017	申请日期	1996.08.02
申请人	OKI ELECTRIC IND CO LTD	发明人	ODAWARA YOSHIKAZU
分类号	H01L21/822;G06F17/50;H01L21/82;H01L27/04;(IPC1-7):H01L21/82	主分类号	H01L21/822
代理机构		代理人
主权项
地址

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