发明名称 |
Method and apparatus for performing timing analysis on a circuit design |
摘要 |
A method and apparatus for efficiently performing timing analysis on a circuit design. The present invention essentially provides a hybrid between a path enumeration algorithm and a critical path algorithm. As such, the present invention increases the number and degree of timing violations reported by a Critical Path Analysis (CPA) algorithm, while maintaining a performance advantage over a Path Enumeration (PE) algorithm. This is accomplished by providing a number of "pseudo" clocks to selected latches within the circuit design database, thereby tricking the CPA algorithm into reporting more timing violations than would otherwise be reported.
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申请公布号 |
US5719783(A) |
申请公布日期 |
1998.02.17 |
申请号 |
US19960597847 |
申请日期 |
1996.02.07 |
申请人 |
UNISYS CORPORATION |
发明人 |
KERZMAN, JOSEPH P.;KURTH, DUANE G.;FULLER, DOUGLAS A. |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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