| 摘要 |
An interface circuit adapted to selectively input serial and parallel PCM coded words and to selectively output serial and parallel PCM coded words is connected to a memory means. The memory means has a storage capacity for at least 2n memory words, each one having an address corresponding to a respective one of the PCM coded words appearing at the interface circuit and each one representing X db of signal level variation relative to its corresponding coded word. The output of the memory means is connected back to the parallel input of the interface circuit. A control means provides timing and control signals for loading the interface circuit with one of the coded words and for causing the memory means to be addressed at the location defined by the coded word. The control means includes means for circulating the coded word through the memory means a predetermined number of times M. The first memory address is defined by the input coded word and every subsequent address is defined by the memory word read out in the previous memory cycle, whereby the output from the circuit is a coded word representing MX db of signal level variation relative to the input coded word. |
