发明名称 Input circuit
摘要 <p>According to the present invention, an input circuit is provided comprising: an input terminal; a first power source terminal; a second power source terminal; a first bipolar transistor; a second bipolar transistor; a first electric current cut off member; a second electric current cut off member; a voltage clamping member; and a buffer. As a result, even when an electric potential greater than that of the power source voltage is applied to the input terminal, regardless of the supply or interruption of the power source voltage, destruction of the internal components is prevented and a steady-state electric current of the power source voltage and/or the input terminal is cut off. Hence, by providing a PMOS transistor and NMOS transistor, which serve to cut off the electric current routes of power source terminal VDD and the ground terminal, in the two bipolar transistors connecting to input terminal 1 to which an input signal greater than the power source voltage is applied, it is possible to cut off the electric current flowing from the power source terminal to the input and ground terminals while also preventing the destruction of the components relating to the increased signal. &lt;IMAGE&gt;</p>
申请公布号 EP0823785(A2) 申请公布日期 1998.02.11
申请号 EP19970113238 申请日期 1997.07.31
申请人 NEC CORPORATION 发明人 WATARAI, SEIICHI
分类号 G11C11/414;H03K19/003;H03K19/0175;(IPC1-7):H03K19/017 主分类号 G11C11/414
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