| 摘要 |
PURPOSE:To provide a fixed data addition/subtraction reduced at its circuit size and shortened at its delay time. CONSTITUTION:The fixed data addition/subtraction is constituted so that the sum output signal of each arithmetic circuit becomes exclusive OR between a data input signal A and control input signal B inputted from a lower bit arithmetic circuit and the value of an output signal CO connected to an upper bit arithmetic circuit becomes an AND value between exclusive OR between the signal A and a control input signal CI for controlling the existence of addition/subtraction execution and a control input signal CO of the lower bit arithmetic circuit and plural arithmetic circuit having the above constitution and corresponding to the necessary number of circuits are sequentially connected. |
