发明名称 |
Logical synthesizing device, logical synthesizing method, and semiconductor integrated circuit |
摘要 |
A logical synthesizing device and logical synthesizing method capable of generating a net list from a feedback loop added flip-flop excellent in layout efficiency. In a cell library, cells of feedback loop added flip-flop are newly registered together with existing various cells. The feedback loop portion of this feedback loop added flip-flop is formed in an optimum layout composition in consideration of the setup time and hold time. A logical synthesizing section, using the cells registered in the cell library, generates a net list for realizing a logical function description, and outputs to a test design section At this time, the feedback loop forming portion in the input and output of the flip-flop generates the net list by using the feedback loop added flip-flop.
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申请公布号 |
US5715171(A) |
申请公布日期 |
1998.02.03 |
申请号 |
US19950533839 |
申请日期 |
1995.09.26 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MORI, YASUFUMI;KOMOIKE, TATSUNORI;HASHIZUME, TAKESHI |
分类号 |
G01R31/28;G01R31/3185;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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