| 摘要 |
PCT No. PCT/GB95/02780 Sec. 371 Date Oct. 1, 1996 Sec. 102(e) Date Oct. 1, 1996 PCT Filed Nov. 29, 1995 PCT Pub. No. WO96/17354 PCT Pub. Date Jun. 6, 1996A memory device with a dynamic random access memory (DRAM) having an array of a plurality of rows and columns of memory elements; a cache memory formed integrally with the DRAM and includinmg at least one register with a plurality of memory elements and connected in pitch-matched relation to the DRAM array, the number of memory elements in a row of the DRAM being n times the number of memory elements in the at least one register, n being an integer greater than or equal to 2; and a connector for connecting the at least one register to the DRAM, the connector for the at least one register being a bus having a width corresponding to the number of memory elements therein.
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