发明名称
摘要 <p>In a semiconductor memory device including ROM cells, a digit line (DL1) for receiving read data from a selected one of the memory cells, and a bias circuit (311) for amplifying a voltage at the digit line, a differential amplifier (313', 313''), which has a positive phase input, a negative phase input, a positive phase output (N1) and a negative phase output (N2), is provided. The positive phase input is connected to the output of the bias circuit. The negative phase output is connected to the negative phase input, thereby establishing a positive feedback loop in the differential amplifier. <IMAGE></p>
申请公布号 JP2705605(B2) 申请公布日期 1998.01.28
申请号 JP19950026177 申请日期 1995.01.20
申请人 发明人
分类号 G11C11/419;G11C7/06;G11C16/06;G11C16/26;G11C17/00;(IPC1-7):G11C11/419 主分类号 G11C11/419
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