CMOS compatible EPROM device

摘要

The specification describes a CMOS compatible process for EPROM manufacture and the resulting EPROM device. The cladding layer used in CMOS processing is utilized in a dual role as a strap for the complementary doped polysilicon gate layer, and as the primary or control gate in the EPROM array. The only additional step in the processing is to form an intergate dielectric to isolate the polysilicon gate on the EPROM side prior to depositing the cladding layer. Using this technique the height of the gate stack not significantly greater than the height of the CMOS gate structures thus resulting in a reduced IC profile.