| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL(phase-locked loop) circuit which can increase its lock-up speed and also can decrease the noises. SOLUTION: This circuit includes an R divider 12 which outputs a 1st signal obtained by applying R division on a reference signal, an N divider 11 which outputs a 2nd signal obtained by applying N division on a feedback signal, a PC 19 which outputs a phase-difference signal between the 1st and 2nd signals, a CP 13 which outputs a charge/discharge signal, based on the phase difference signal, a loop filter 14 which outputs a control signal based on the charge/ discharge signal, a VCO 15 which outputs the feedback signal, based on the control signal, and a mode controller 18 which controls the phase comparison frequency of both dividers 11 and 12 to turn them into a frequency 2n-times as high as a steady mode in a fast mode and also controls the phase comparison sensitivity of the CP 13, to turn it into a 1/2n-multiple level, respectively. |
