发明名称 Shared buffer memory switch for an ATM switching system and its broadcasting control method
摘要 A shared buffer memory switch for an ATM switching system and its broadcasting control method are provided which can guarantee the cell transfer quality defined for each connection by maintaining the sequence order of arrival for each cell even if ordinary and broadcasting cells are mixed. When an input cell is a broadcasting cell, bit map data showing a broadcasting destination information is read from a broadcast registration table (6) based on the routing information derived from a header information of the cell, and an address for storing the cell in the shared buffer memory (3) is written in all the address pointer queues of FIFOs (9-) corresponding to all output ports shown in the broadcasting destination information, and the cell is stored in the shared buffer memory (3) with the broadcasting destination information. In reading a cell, an address of the shared buffer memory from which the cell is to be read out is read from the address pointer queue of FIFO(9-), and the cell is output to the corresponding output port. In the case where the cell is a broadcasting cell, the broadcasting destination information attached to the cell is reset for the corresponding output port and the revised broadcasting destination information and the cell is stored in the same address of the shared buffer memory until all broadcasting destination information are reset. (Fig. 7) <IMAGE>
申请公布号 AU685606(B2) 申请公布日期 1998.01.22
申请号 AU19950020250 申请日期 1995.05.23
申请人 NEC CORPORATION 发明人 KENJI YAMADA
分类号 H04Q3/00;H04L12/18;H04L12/70;H04L12/931;H04Q11/04 主分类号 H04Q3/00
代理机构 代理人
主权项
地址