Support cache-memory for semiconductor memory

摘要

The integrated cache-memory chip (500) stores data in a main DRAM memory (300) and a cache SRAM (310). A Cache Address Memory (320) marks addresses of data held in SRAM. Almost simultaneous presentation of column and row addresses to the correlation detector (320, 340) produces a cache hit/miss (H/M) signal depending on correlation or otherwise of external micro-processor addresses with those in CAM. A cache-hit results in direct writing or reading of SRAM. A miss results in writing or reading of DRAM via SRAM (refresh mode) through a data transfer device IFD (330).