发明名称 |
Parallel architecture for a high definition television video decoder having multiple independent frame memories |
摘要 |
A parallel decoder for an MPEG-2 encoded video signal includes a deformatter which separates the input bit stream into multiple portions, each representing a respectively different section of the HDTV image. The separate portions are processed in parallel by respective decoders. In order to perform motion compensated processing, each of the four decoders includes a memory that holds data representing the entire image. Each decoder provides its decoded output data to all of the decoders to maintain the data in the respective memories. <IMAGE> |
申请公布号 |
EP0710026(A3) |
申请公布日期 |
1998.01.21 |
申请号 |
EP19950108437 |
申请日期 |
1995.06.01 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
PHILLIPS, LARRY;NAIMPALLY, SAIPRASAD V.;MEYER, EDWIN ROBERT;INOUE, SHUJI |
分类号 |
H04N11/04;G06T9/00;G09G5/39;H03M7/36;H04N5/44;H04N7/015;H04N7/26;H04N7/30;H04N7/32;H04N7/50;H04N7/56 |
主分类号 |
H04N11/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|