Single polysilicon level flash EEPROM cell and manufacturing process therefor

摘要

A flash EEPROM memory cell comprises source and drain regions (71,72,81,82;73,83) defining a channel region therebetween, a floating gate (10) and a control gate (9). The source and drain regions are first and second doped semiconductor regions (71,72,81,82;73,83) of a first conductivity type formed in a first active area region (33) of a semiconductor material layer (1) of a second conductivity type; the control gate comprises a third doped semiconductor region (9) of the first conductivity type formed in a second active area region (34) of the semiconductor material layer (1); and the floating gate comprises a polysilicon strip (10) insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region (9). <IMAGE>