发明名称 Tungsten silicide polycide gate electrode formed through stacked amorphous silicon (SAS) multi-layer structure.
摘要 A method for forming a tungsten silicide polycide gate electrode within a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the tungsten silicide polycide gate electrode which is formed through the method. Formed upon a semiconductor substrate is a gate oxide layer. Formed upon the gate oxide layer is a first polysilicon layer which is formed through annealing a first amorphous silicon layer. Formed upon the first polysilicon layer is a second polysilicon layer which is formed through annealing a second amorphous silicon layer. Formed upon the second polysilicon layer is a tungsten silicide layer formed through a Chemical Vapor Deposition (CVD) method. The first polysilicon layer and the second polysilicon layer have a crystallite size no greater than about 0.3 microns, and the first polysilicon layer and the second polysilicon layer have a dopant concentration larger than about 1E16 atoms per cubic centimeter. Optionally, at least a third polysilicon layer may be added through annealing at least a third amorphous silicon layer between the second polysilicon layer and the tungsten silicide layer. Optionally, an fourth amorphous silicon layer may be added directly beneath the tungsten silicide layer.
申请公布号 US5710454(A) 申请公布日期 1998.01.20
申请号 US19960638671 申请日期 1996.04.29
申请人 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION 发明人 WU, SHYE LIN
分类号 H01L21/28;H01L29/49;(IPC1-7):H01L29/76;H01L21/44 主分类号 H01L21/28
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