| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of layers of a flip chip package by aligning a first voltage source trace on a first conductive layer with an I/O trace on a second conductive layer and a second voltage source trace on the second conductive layer with an I/O trace on the first conductive layer. SOLUTION: A die 10 carrying an integrated circuit 12 on the front surface side is bonded to a substrate 30 in a die bonding area 38 with the front surface, namely, the surface carrying the integrated circuit 12 of the die 10 on the downside. The substrate 30 is constituted of a first conductive layer 32, dielectric layer 34, and second conductive layer 36. A first voltage source trace on the first conductive layer 32 is aligned with an I/O trace on the second conductive layer 36 and a second voltage source trace on the layer 36 is aligned with an I/O trace on the layer 32. Therefore, the number of layers of a flip chip package can be reduced without deteriorating the electrical characteristic of the package. |
