| 摘要 |
PROBLEM TO BE SOLVED: To make a circuit easily applicable to a semiconductor integrated circuit through the configuration with only a digital circuit and to contribute to a high speed operation by decreasing a time till synchronization is established. SOLUTION: The phase synchronization circuit where an external clock signal is synchronized with an internal clock signal is provided with 1st and 2nd delay lines 4, 8 having the equal delay to a period T of the external clock signal, a delay circuit 3 delaying the external clock signal by a prescribed time (d) to provide the result to the 1st delay line 4, a pulse generating circuit 5 converting the external clock signal into a pulse signal, and a transfer circuit 7 transferring the clock signal from the 1st delay line 4 to the 2nd delay line 8 depending on the pulse signal generated by the pulse generating circuit 5, and the clock signal is extracted from the 2nd delay line 8 to generate the internal clock signal delayed by 2T with respect to the external clock signal. |
