| 摘要 |
A dual-directional parallel processor. The inventive processor (10) includes an array (20) of processing elements (30). Each processing element has a first circuit (31) for inputting and outputting data, a second circuit (32) for inputting and outputting data; and a third circuit (33, 34) for setting the first circuit (31) in an input mode and for setting the second circuit (32) in an output mode in response to a first mode control signal. The third circuit (33, 34) also sets the first circuit (31) in an output mode and the second circuit (32) in an input mode in response to a second mode control signal. In the illustrative embodiment, data is communicated between the first and the second circuits (31, 32) and the processor further includes a fifth circuit (12) for inputting data to the array and a sixth circuit (14) for outputting data from the array. Each of the processing elements (30) is connected either between two other processing elements or between the fifth circuit (12) or the sixth circuit (14) and a neighboring processing element via the first or the second circuit (31 or 32) thereof.
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