| 发明名称 |
REDUCED PARASITIC CAPACITANCE SEMICONDUCTOR DEVICES |
| 摘要 |
The present invention relates to a technique for reducing parasitic capacitances in high speed Schottky barrier and p-n junction devices. A structure for a semiconductor device having a substrate, a semiconductor device disposed on the substrate, and a bond pad (405) in electrical contact with the device. A layer of BCB is disposed about the device, and the bond pad (405) is disposed on a top surface of said BCB. |
| 申请公布号 |
WO9800866(A1) |
申请公布日期 |
1998.01.08 |
| 申请号 |
WO1997US11083 |
申请日期 |
1997.06.25 |
| 申请人 |
THE WHITAKER CORPORATION;ANAND, YOGINDER;CHINOY, PERCY, BOMI |
发明人 |
ANAND, YOGINDER;CHINOY, PERCY, BOMI |
| 分类号 |
H01L29/872;H01L21/60;H01L21/768;H01L23/29;H01L23/31;H01L23/485;H01L23/522;H01L23/66;H01L29/47 |
主分类号 |
H01L29/872 |
| 代理机构 |
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