发明名称 Method and apparatus for enabling pipelining of buffered data
摘要 A system that enables pipelining of data to and from a memory includes multiple control block data structures which indicate amounts of data stored in the memory. An input port device receives and stores in memory, data segments of a received data message and only updates status information in the software control blocks when determined quantities of the data segments are stored. An output port is responsive to a request for transmission of a portion of the received data and to a signal from the input port that at least a first control count of data segments of the received data are present in memory. The output port then outputs the stored data segments from memory but discontinues the action if, before the required portion of the received data is outputted, software control blocks indicate that no further stored data segments are available for outputting. The input port then updates the software control blocks when newly arrived and stored data segments reach a second control count value, the updating occurring irrespective of whether the determined quantity of the received data has been stored in memory.
申请公布号 US5706443(A) 申请公布日期 1998.01.06
申请号 US19940241904 申请日期 1994.05.11
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BRADY, JAMES T.;FINNEY, DAMON W.;HARTUNG, MICHAEL H.;LANG, DONALD J.;MENON, JAISHANKAR M.;NOWLEN, DAVID R.;TANG, CALVIN K.
分类号 G06F13/12;G06F5/06;G06F13/38;(IPC1-7):G06F13/00 主分类号 G06F13/12
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