| 摘要 |
A memory device for processing a block of digital video signal data comprises a random block access (RBA) controller for generating a system control signal to thereby vary a size of the block, an address generator for receiving external address signals according to the system control signal generated by the RBA controller to thereby generate internal addresses corresponding to the size of the block, a memory cell array to which digital video signal data is written or from which digital video signal data is read according to the internal addresses generated by the address generator, a transmission controller for controlling the transmission of digital video signal data stored in the memory cell array corresponding to the internal addresses generated by the address generator, an input/output unit for receiving or sending digital video signal data outside the memory device under the control of the RBA controller and the transmission controller.
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