A METHOD AND APPARATUS FOR PROVIDING CONCURRENT ACCES BY A PLURALITY OF AGENTS TO A SHARED MEMORY

摘要

A computer system (10), including a graphics controller (18) and a memory controller (14), employs a Shared Frame Buffer Architecture, and accordingly has a shared memory (20) in the form of a bank of DRAMs. The shared memory (320) is accessible by both the memory and graphics controllers. The selector circuit is operable by a logic circuit (231), incorporated within the systems controller (230), which determines whether a memory access request received from the memory controller is to an address in the shared DRAM row (220.2).