| 摘要 |
A data processor (3) executes a breakpoint operation before an exception processing routine for a reset operation is initiated. When an External Reset signal is asserted and subsequently negated, a window of time exists in which data processor (3) is quiescent before beginning an actual reset exception processing routine. If an external breakpoint signal, +E,ovs BKPT+EE is asserted during a quiescent time by external development system (7), data processor (3) downloads a target memory value into a memory (6) such that any hardware register configuration may be performed.
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