| 摘要 |
In a device controlled by an original control signal for correcting a header error in an original STM signal comprising first through P-th header blocks and an HEC (header error check) block, each header block comprising first through N-th ATM cell header units, the HEC block comprising first through N-th ATM cell HEC units, a delay circuit (49) produces a delayed STM signal (S') by giving the original STM signal (S) a delay equal to (P x N) times an interval of each of the header and the HEC units. Another delay circuit (51) produces a delayed control signal (C') by giving the original control signal (C) the delay. In accordance with an n-th check result produced by an error checking section (43, 45, 47) controlled by the original control signal to check the header error in the original STM signal, an error correcting section (53, 55, 59, 61) corrects the header error in connection with an n-th ATM cell header unit of a p-th header block of the delayed STM signal when the delayed control signal indicates the n-th ATM cell header unit of the p-th header block, where n and p are variable between 1 and N (both inclusive) and between 1 and P (both inclusive), respectively. |
