| 摘要 |
<p>A programmable logic output driver includes a bias generator (100), a current mirror (200) and an output stage (300), there being a digital programming feature to maintain the output voltage slew rate at an acceptable value for either high or low values of load capacitances. The driver is programmable and can maintain a constant value of driver output resistance in the circumstances where the load voltage approaches the full swing logic voltage. In the preferred embodiment, the programmed output resistance is independent of variations in process, temperature and VDD supply voltage. TTL loads are driven with the minimum amount of required output current. Because of the constant resistance, the driver supplies a specified amount of current to the load even when the load is pulled down to a specified voltage. The resistance value is substantially the highest value possible consistent with providing a required minimum load drive current and the resistive damping of the output RLC circuit is maximized so that voltage "kick" or "undershoot" is held to a minimum. <IMAGE></p> |
