| 摘要 |
An improved input ESD protection structure is disclosed that is suitable for use on high-voltage input pins, such as programming pins, of programmable integrated circuits such as programmable logic devices (PODs) programmable read-only memories (PROMs), or field programmable gate arrays (FPGAs). The input ESD protection structure includes a primary ESD protection FET for shunting ESD current from the input pad, and a secondary ESD protection FET, in combination with a series resistor, to limit the voltage appearing across the gate oxides of the input buffer. The primary protection FET is laid out in a multi-finger architecture wherein the drain n+-type conductivity regions are overlapped with a depletion implant. The depletion implant extends from these drain regions, respectively, through channel regions toward the source regions. Further, the ESD protection structure is subject to a p-well mask, which blocks the formation of a p-well to thereby reduce background p-type doping to p-substrate doping levels. The depletion implant and p-well protect mask increase the breakdown, and snapback voltages of the primary and secondary FETs to improve ESD immunity. An n-well is disposed underneath the drain region, particularly under the drain contacts, to increase the junction depth in the drain region to thereby minimize contact spiking during an ESD event. The secondary protection FET is integrated with the primary protection FET by using the same n+diffusions as used by the primary ESD protection FET.
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