| 摘要 |
PROBLEM TO BE SOLVED: To increase the operating speed of a logic integrated circuit device, etc., containing a serial to parallel converter incorporating an edge trigger type flip flop and to reduce the cost of the device, etc., by increasing the operating speed of the circuit and reducing the layout area of the circuit. SOLUTION: A serial to parallel converter incorporated in a logic integrated circuit device, etc., is constituted of a master latch ML which also has the function of a differential input buffer which fetches input signals Vin of a small amplitude, fetches the input signals Vin in accordance with the substantial OR signal of, for example, two phases of clock signals CK1 and CK2, the high- level periods of which do not overlap each other, and holds the signals Vin with a small amplitude which is close to that of the signals Vin and, for example, two slave latches SL1 and SL2 which successively and alternately fetch the output signal nb of the master latch ML in accordance with the clock signal CK1 or CK2. At the same time, the master latch ML and slave latches SL1 and SL2 are arranged in an I/O cell arranging area in which the arranging positions of logic elements are restricted to the vicinities of their corresponding pads. |
