SPEED CONVERSION CIRCUIT AND DATA TRANSMITTER USING IT

摘要

PROBLEM TO BE SOLVED: To provide the speed conversion circuit which provides a small change in data delay or a small data delay even when a data speed is changed and to provide the data transmitter using the circuit. SOLUTION: Registers 2, 7 decide an address upper limit (buffer capacity) of a memory 1 based on write speed information WI and read speed information RI with respect to the memory 1. Comparators 3, 8 reset/hold each counter when a write address WA and a read address RA of a memory 1 generated by a write address generating counter 6 and a read address generating counter 9 are coincident with address upper limit values. A write address initializing circuit 5 generates a pulse signal to have a delay as near as possible to a minimum delay time at a highest speed operation based on the write speed information WI or the like and writes the signal and resets the address WA to decide the data delay.