| 摘要 |
PROBLEM TO BE SOLVED: To improve the efficiency of processing operation execution by performing control from a control means to respective transfer means so that the transfer means to execute the transfer of the processing result can be turned into data through state when the execution of processing procedures at respective processing means is finished. SOLUTION: The switching of data through state and holding state at latches 2a-2e is controlled by double phase clock signalsϕ1 andϕ2. Therefore, when the execution of substages A1, A2, B1 and B2 at respective logics 1a-1d is finished even while processing time is not equal for the plural logics 1a-1d, the latches 2a-2e to transfer the processing result are turned into data through state so that the processing result can be immediately transferred to the logics 1a-1d to execute the next substages A1, A2, B1 and B2. Thus, no dead time is generated within stages A and B until the processing operations on the respective stages A and B of respective substages A1, A2, B1 and B2 are completed.
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