| 摘要 |
A high-speed sense amplifier for a semiconductor memory device which has a plurality of memory cells and true and complementary bit lines connected to the memory cells, comprising first and second PMOS transistors cross coupled between the true and complementary bit lines, for sensing and amplifying true and complementary data on the true and complementary bit lines, to be restored in a corresponding one of the memory cells, the first and second PMOS transistors commonly inputting a high voltage signal; first and second NMOS transistors cross coupled between the true and complementary bit lines, for sensing and amplifying true and complementary data on the true and complementary bit lines, transferred from the corresponding memory cell, the first and second NMOS transistors commonly inputting a low voltage signal; and a voltage regulation circuit for regulating a back bias voltage to the first and second NMOS transistors in response to a voltage control signal to vary threshold voltages of the first and second NMOS transistors. According to the present invention, a substrate voltage and a ground voltage are selectively used as the back bias voltage to the first and second NMOS transistors to regulate the threshold voltages of the first and second NMOS transistors.
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