发明名称 MULTIPLIER AND DIGITAL SIGNAL PROCESSOR USING THE SAME
摘要 PROBLEM TO BE SOLVED: To speed up single-precision multiplication without increasing the amount of hardware, to process the multiplication (single-precision multiplication) of n-bits ×n-bits with one cycle and the multiplication (double-precision multiplication) of 2n-bits × 2n-bits with four cycles, for example. SOLUTION: A partial product generation circuit 301 having a first control mode (single-precision multiplication mode) generating n/2-pieces of partial products at once and a second control mode (double-precision multiplication mode) generating n/4-pieces of partial products at once from a multiplicand and a multiplier, adders 302 and 303 in a fist stage, which add the partial products generated in the partial product generation circuit 301, selection circuits 305-310 selecting the output of the adders 302 and 303 in the first stage based on the first control mode or the second control mode and adders 311 and 312 in a second stage, which add the outputs of the selection circuits 305-310 are provided.
申请公布号 JPH09311779(A) 申请公布日期 1997.12.02
申请号 JP19960129483 申请日期 1996.05.24
申请人 HITACHI LTD;HITACHI VLSI ENG CORP 发明人 OGATA YASUHIRO;KIUCHI ATSUSHI;IMAI NORITSUGU;NISHIYAMA KUNIHIKO;NOGUCHI YOSHIKI
分类号 G06F7/53;G06F7/506;G06F7/52;G06F7/525;G06F7/533 主分类号 G06F7/53
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