| 摘要 |
This is a PLL frequency synthesizer having a reference divider for dividing a reference source signal, and an RF divider for dividing the output of a voltage controlled oscillator, wherein when changing over the frequency, first the division value of the RF divider changes periodically to become a fractional division value in average, and after the frequency is nearly changed over, the RF divider is set in a conventional integer division operation, therefore, the frequency can be changed over at high speed by the fractional division operation high in reference frequency, and after the changing, a low spurious signal characteristic may be realized.
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