X MAIN DECODER CIRCUIT

摘要

PROBLEM TO BE SOLVED: To keep an operational speed at the same extent as usual, to reduce a transistor size and signal wiring, to suppress a layout occupancy area and to reduce a circuit area by providing a CMOS transistor, etc., in a word decoder circuit. SOLUTION: The word decoder circuit 11 is provided with N channel and P channel MOS transistors 6, 7 constituting a CMOS transfer gate, a switching transistor 8 for charge and an inverter 9 driving a gate of a memory cell. Thus, in the word decoder circuit 11, since the inverter 9 driving a memory cell selection line E is an initial stage of the P channel MOS transistor from source potential, a gate width is reduced to 1/2 compared with the usual gate width when the operational speed is made almost the same. Further, the number of control signal is reduced to 1/2, and the deterioration of the operational speed is suppressed, and the layout area is reduced.