FORMATION OF FLAT PATTERN, FLAT PATTERN FORMING APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PROBLEM TO BE SOLVED: To enable a formed flat pattern to satisfy rules of wiring pattern layout design and also enable the number of figures in the flat pattern and a data amount to be both suppressed. SOLUTION: A wiring pattern is expanded by a predetermined amount to produce an enlarged wiring pattern, and after that, the parts of a first dummy original pattern of square sets overlapped with the enlarged wiring pattern are eliminated from the original pattern to form a dummy pattern. The dummy pattern is reduced by a predetermined amount C to form a reduced dummy pattern 14, and then the reduced dummy pattern 14 is enlarged by the predetermined amount C to form a flat pattern 15. A wiring pattern 11 is combined with the flat pattern 15 to form such a final pattern as shown in (c).