High performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory address

摘要

An access hazard detection technique in a pipelined cache controller sustains high throughput in a frequently accessed cache but without the cost normally associated with such access hazard detection. If a previous request (request in the pipeline stages other than the first stage) has already resulted in a cache hit, and it matches the new request in both the Congruence Class Index and the Set Index fields and if the new request is also a hit, the address collision logic will signal a positive detection. This scheme makes use of the fact that (1) the hit condition, (2) the identical Congruence Class Index, and (3) the Set Index of two requests are sufficient to determine that they are referencing the same cache content. Implementation of this scheme results in a significant hardware saving and a significant performance boost.