发明名称 Generic gate level model for characterization of glitch power in logic cells
摘要 According to the present invention, there is provided a method for determining glitch power in a logic circuit having a power supply terminal, a first input, a second input, and an output coupled to a capacitive load. In one embodiment, the method includes: determining at least one ramp time sum, each ramp time sum corresponding to a pair of ramp times; determining a plurality of separation times by: selecting a minimum separation time, selecting a maximum separation time, dividing a difference between the minimum separation time and the maximum separation by a step value to determine a separation time increment, incrementing the minimum separation time by multiples of the separation time increment until the incremented minimum separation time approximately equals the maximum separation time; determining an average current flowing through the power supply terminal for each separation time and ramp time sum; storing the average current in a computer-readable medium; and interpolating an actual average current from the stored average current values based upon actual ramp times and an actual separation time.
申请公布号 US5691910(A) 申请公布日期 1997.11.25
申请号 US19960661186 申请日期 1996.06.10
申请人 LSI LOGIC CORPORATION 发明人 THODIYIL, JOHN A.
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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