| 摘要 |
In a DRAM having a dummy bit line in a memory cell array, a column decoder enable signal generator detects the voltage level of the dummy bit line and uses it as column decode enable signal when data of the bit line is sensed, thereby removing unnecessary timing margin during sensing operation to improve access time. The column decoder enable signal generator includes a sensing amplifier for sensing and amplifying data of the bit line, a sensing amplifier enable signal generator for generating a signal which controls the operation of the sensing amplifier, a detector for detecting the voltage level of the dummy bit line, and a column decoder for selecting a cell corresponding to the column address using the output signal of the detector and column address output signal.
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