| 摘要 |
PROBLEM TO BE SOLVED: To determine the operating timing of an output buffer by enabling an output control signal to be arbitrarily set by prescribed input signals to select an optimum pulse from among plural pluses of synchronizing clocks. SOLUTION: A data latching circuit 601 latches readout data S1 read out on data busses 119 to apply them to an output circuit 123. The circuit 123 is activated by an output control signalϕa synchronized with a clock signal CLK and reads out the data S1 to output them in the form of data D0. In this case, a memory control signal generating circuit 125 and an output clock delay control circuit 607 are provided in this DRAM and the circuit 125 outputs a memory control signal S3 controlling the inside of the memory and a drive signal S4 by inputting signals CLK, the inverse of RAS and the inverse of CAS to be inputted from the outside. The circuit 607 receives signals CLK, the inverse of RAS, S4 and external input signals SEL0 and SEL1 to generate the output control signalϕa controlling the output circuit 123 optimally by arbitrarily selecting the signals SEL0, SEL1.
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