发明名称 |
Apparatus and method for controlling instruction flow by using a matrix of transmission gates in super-scaler microprocessor and selectively delaying microprocessor instruction execution based on resource availability |
摘要 |
An instruction flow control circuit controls the selection and execution of instruction signals in a microprocessor having multiple execution units that can execute plural instructions at one time. The instruction flow control circuit compares a number of signals indicating how many execution units are available with a number of signals indicating how many execution units are required. The circuit is a matrix of transmission gates which propagate signals through, or shift signals between, various signal paths for available resources, depending on the signals requesting the executing units. A number of output gates suppress the execution of instruction signals where an execution unit is requested but none are available. |
申请公布号 |
US5689673(A) |
申请公布日期 |
1997.11.18 |
申请号 |
US19950388602 |
申请日期 |
1995.02.14 |
申请人 |
HAL COMPUTER SYSTEMS, INC. |
发明人 |
KITAHARA, TAKESHI |
分类号 |
G06F9/38;(IPC1-7):G06F13/14;G06F9/22;G06F9/30 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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