| 摘要 |
Mutually Exclusive Gating (MEG) requirements arising from the use of level Sensitive Scan Design (LSSD) rules are satisfied for handling clock phase conflicts in an integrated circuit design. Automatic generation of test patterns for hardware testing of a manufactured integrated circuit is completed without adding logic to the integrated circuit's design. The automatic test pattern generation (ATPG) system identifies and traces cones of logic from a detailed description of an integrated circuit's design. The system also identifies portions of cones that are functional data, clock, and enable input nets. Multiple cones are grouped into partitions. During partitioning, input latches of a cone being driven by the same functional clock as an apex latch of the cone are identified. A net list is created for each partition. Input latches and apex latches having common functional clocking are replaced by 2-1 selectors and AND gates in the ATPG's internal data structures to produce the MEG condition, thereby allowing correct test pattern generation without addition of logic to the circuit design.
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