| 摘要 |
PROBLEM TO BE SOLVED: To provide the clock extract circuit able to extract a clock signal stably and quickly even when input digital signals are extremely localized toward 1s or 0s. SOLUTION: The circuit is provided with a synchronization pattern detection circuit 3 receiving an input digital signal, a Q value control circuit 4 connecting to the synchronization pattern detection circuit and a digital PLL circuit 1, and a unique word(UW) detection circuit 5 receiving the input digital signal and extracted clock to control the operation of the digital PLL circuit 1. The synchronization pattern detection circuit 3 receives the input digital signal to detect a specific synchronization pattern and provides an output of a pattern detection signal. The Q value control circuit 4 controls the Q of the digital PLL circuit 1. The UW detection circuit 5 receives the input digital signal and the extracted clock and stops the synchronization processing of the digital PLL circuit 1 when a specific UW is detected. |
