发明名称 CLOCK EXTRACT CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain the clock extract circuit with excellent response in the case of extracting a clock with a file device using an optical disk or a magnetic disk or the like with a wide capture range. SOLUTION: A reproduction signal 11 read from a disk or the like is given to a phase error extract circuit 12 together with an extract clock 19, a synchronization flag 21 outputted from a synchronization discrimination circuit 13 and a rate flag 22 outputted from a rate comparator circuit 14. When the frequencies are coincident, a phase error is obtained similarly to the case with a conventional phase comparator and a loop filter 16 and a voltage controlled oscillator 18 obtain the extract clock 19. When the frequencies are dissident, a phase error signal with a polarity designated by the rate flag 22 is outputted and the frequency of the extract clock 19 is controlled to be close to the data rate of the reproduction signal 11 automatically.
申请公布号 JPH09284269(A) 申请公布日期 1997.10.31
申请号 JP19960098022 申请日期 1996.04.19
申请人 NEC CORP 发明人 KAYANUMA KINJI
分类号 G11B20/14;H03L7/08;H04L7/033;H04L25/40 主分类号 G11B20/14
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