CHANGE TIMING DETECTION CIRCUIT AND BIT PHASE SYNCHRONIZATION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To detect a change timing of received data sufficiently even when a circuit element having a high speed leading or trailing performance is not employed in the case of reception of even a high speed digital signal. SOLUTION: A sampled output signal D31 from a D flip-flop circuit DFF31 based on a clock CLK2 is given to a DFF32. A sampled output signal D32 from a D flip-flop circuit DFF32 receiving the sample output signal D31 based on a clock CLK1 is given to a DFF33. A sampled output signal D33 from a D flip-flop circuit DFF33 receiving the sample output signal D32 based on a clock CLK0 is given to a CLK0 system synchronization circuit 1. A phase difference of 2T/3 is in existence between the sample output signals D31 and D32 and a phase difference of 2T/3 is in existence between the sample output signals D32 and D33.