发明名称 |
Channel structure of field effect transistor and CMOS element |
摘要 |
<p>A field effect transistor is fabricated on an SOI substrate. N-type source and drain regions are arranged apart from each other in a semiconductor thin film of the SOI substrate. A P-type channel region is formed between the source and drain regions. Moreover, a gate electrode is formed over the channel region to cover the channel region through a gate oxide film. Extreme portions of the channel region, adjacent to the source and drain regions, have higher doping concentrations than in a center portion thereof. Furthermore, the gradient of the doping profile in the channel region is adjusted so as to reduce the current gain of a parasitic transistor in the field effect transistor. This structure enables a reduction of the channel length of the field effect transistor to the sub-half-micron order without deteriorating the electrical characteristics of the field effect transistor. <IMAGE></p> |
申请公布号 |
EP0803911(A2) |
申请公布日期 |
1997.10.29 |
申请号 |
EP19970300392 |
申请日期 |
1997.01.22 |
申请人 |
SHARP KABUSHIKI KAISHA |
发明人 |
ADAN, ALBERTO OSCAR;KANEKO, SEIJI |
分类号 |
H01L21/336;H01L21/84;H01L27/12;H01L29/786;(IPC1-7):H01L29/786 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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