| 摘要 |
A semiconductor test system is to realize a pattern generation that makes possible to test memory devices having arbitrary cycle latency operations when using multiple pattern generators. A cycle shift circuit that outputs a delayed expected value signal by shifting the expected value by one cycle with the operating period of the pattern generator is arranged. A N to 1 selector that selects an arbitrary signal from the expected value signal output by the multiple pattern generators including itself and the delayed expected value signal output by the multiple pattern generators excluding itself is arranged. A cycle shift section is arranged for the output selected by the selector. An arbitrary cycle shift can be generated by the expected value pattern using the above multiple pattern generators. In further aspect, a semiconductor test system includes a pattern generator having a pattern generation section that generates the driver pattern and expected value signal and a cycle shift section that shifts the expected value signal, a waveform shaper that outputs the driver waveform to the memory using a clock signal, and multiple phase converters that generate the expected value pattern by shifting the expected value shift signal with an operating cycle of the memory generated by a period generator, a phase converter, and a timing generator having a timing shift section that generates a strobe signal shifted by the number of cycles by the latency operations, a logical comparator that compares the cycle delayed output data generated from the memory with the expected value pattern at the timing of the strobe signal. |
