| 摘要 |
<p>A redundancy memory register for storing defective addresses of defective memory elements in a memory device comprises a plurality of memory units (MU0-MU10) each one storing a respective defective address bit and comparing the defective address bit stored therein with a respective current address bit (RA0-RA10) of a current address supplied to the memory device. The register comprises a first group (G1) of memory units (MU4-MU10) and a second group (G2') of memory units (MU0-MU3) storing a first defective address, and a third group (G2'') of memory units (MU0-MU3) storing, together with the first group, a second defective address which has an address part (RA4-RA10) in common with the first defective address. The first and second group of memory units supply first redundancy selection means (15,16,18,SW1,DA) for selecting a first redundancy memory element (RWA) when the current address coincides with the first defective address. The first and third group of memory units supply second redundancy selection means (17,18,SW2,DB) for selecting a second redundancy memory element (RWB) when the current address coincides with the second defective address. The register comprises first address configuration detection means (1) for detecting if the current address coincides with a default configuration stored in the first and second group of memory units and for correspondingly deactivating the first and second redundancy selection means, and second address configuration detection means (2) for detecting if the current address coincides with a default configuration stored in the third group of memory units and for consequently deactivating the second redundancy selection means. <IMAGE></p> |
